This tutorial visualizes an N-Channel Enhancement-Mode MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Unlike the BJT, which is current-controlled, the MOSFET is purely voltage-controlled: the Gate is insulated from the body by a thin oxide layer, so Gate current is zero. A positive Gate voltage creates an inversion layer (N-channel) that connects Source and Drain.

 

Mathematical foundation

1. Structure

Body (P-type): Substrate with holes. Source and Drain (N-type): Two wells. Gate: Metal (or poly) above the body, separated by SiO₂ (insulator). No direct current path to the Gate.

2. Threshold (V_th)

When V_gs < V_th, the body blocks current. When V_gs > V_th, the positive Gate repels holes and attracts electrons to the surface, forming a thin N-channel (inversion layer) under the oxide.

3. Square-law model

In saturation (V_ds ≥ V_gs − V_th) the drain current follows the square law; in the triode (linear) region it is parabolic in V_ds:

4. Transconductance

The small-signal gain of the device, with effectively infinite input impedance (I_g = 0):

Simulation

The interactive simulator is below. Use the controls to explore the concepts described above.

 

Usage

Use the sliders and Source to explore the N-Channel MOSFET:

1. Source: DC (constant V_gs, V_ds), Sinusoidal, or Pulse Train. For non-DC, DC Offset and AC Amplitude set the Gate drive.
2. V_gs (0–5 V): Gate-Source voltage. Above V_th ≈ 2 V the channel forms; blue electrons flow from Source to Drain.
3. V_ds (0–10 V): Drain-Source voltage. In triode (low V_ds) current rises with V_ds; in saturation (V_ds ≥ V_gs − V_th) the channel pinches off and I_d is roughly constant.
4. Top canvas: P-body (light red), N-wells (blue) for Source and Drain, white oxide, grey Gate. Blue dots = electrons in the channel; red circles = holes in the body.
5. Middle: I_d vs V_ds for several V_gs. Dashed curve = saturation boundary. Red dot = operating point.
6. Scope: Yellow = V_gs; Cyan = V_out (load resistor). I_g = 0.00 nA always (Gate is insulated).

Lab trials

Lab 1: The Threshold Hunt

Objective: Find the V_gs where the channel "snaps" into existence.

Setup:

• Source: DC
• V_ds: 5.0 V (fixed)
• V_gs: Start at 1.0 V and slowly increase.

What to Observe:

• Below ~2.0 V: The area under the oxide is empty. No electrons cross; I_d = 0.
• Above ~2.1 V: A thin "bridge" of blue particles suddenly forms under the Gate. This is the inversion layer (N-channel).
• Physics: The positive Gate repels holes and attracts electrons to the surface, creating the channel.

Lab 2: Ohmic vs. Saturation (The Water Hose)

Objective: See how V_ds affects the channel shape.

Setup:

• Source: DC
• V_gs: 3.5 V
• V_ds: Start at 0 V and increase to 10 V.

What to Observe:

• Linear (triode): At low V_ds, the channel looks like a uniform blue bridge. I_d increases with V_ds.
• Pinch-off: As V_ds approaches V_gs − V_th, the channel narrows near the Drain.
• Saturation: The channel is wedge-shaped (thick at Source, thin at Drain). I_d stays nearly constant; particles "sprint" through the pinched region.

Lab 3: The Perfect Switch

Objective: Use a Pulse Train to show why MOSFETs dominate digital circuits.

Setup:

• Source: Pulse Train
• DC Offset: 1.5 V, AC Amplitude: 2.0 V (input snaps between 0.5 V = Hard OFF and 3.5 V = Hard ON)
• V_ds: 5.0 V
• Wave speed: 0.10 Hz

What to Observe:

• Scope: Output inverts the input (logic inverter).
• I_g = 0.00 nA: The Gate draws no current. Compare to a BJT, where I_b is always non-zero. MOSFETs don't get as hot in digital circuits because there is no Gate current.

Lab 4: The High-Fi Amplifier

Objective: Observe how a small wiggle in V_gs creates a large, inverted wiggle in V_out.

Setup:

• Source: Sinusoidal
• DC Offset: 2.5 V (biasing just above V_th)
• AC Amplitude: 0.2 V
• V_ds: 5.0 V

What to Observe:

• Phase inversion: The Cyan wave (V_out) goes down when the Yellow wave (V_gs) goes up.
• Voltage gain: Compare the heights of the two waves. The MOSFET acts like a "magnifying glass" for the signal.
• Physics: Watch the blue channel "breathe"—getting thicker and thinner—without ever fully disappearing.

Lab 5: Frequency Response & Lag

Objective: Discover the physical speed limits of a transistor.

Setup:

• Source: Pulse Train (use Lab 3 settings: DC Offset 1.5 V, AC Amplitude 2.0 V)
• Wave speed: Start at 0.10 Hz and increase toward 2 Hz

What to Observe:

• The lag: At high speeds, the red holes can't "return" to the surface fast enough before the next pulse. The channel doesn't fully form or collapse.
• Signal degradation: On the scope, the Cyan pulses lose sharp corners and start looking like rounded "sharks' fins."
• Conclusion: This is why your CPU gets hot and has a clock-speed limit—physics takes time!

Summary

Vgs	Vds	Region	Use
< Vth	Any	Cutoff	Switch OFF
> Vth	< Vgs − Vth	Triode (Ohmic)	Resistor / switch ON
> Vth	≥ Vgs − Vth	Saturation	Amplifier / current source

Limitations

• Ideal square-law model. Uses the textbook I_d = K(V_gs−V_th)² law. It omits channel-length modulation (λ), velocity saturation, sub-threshold (weak-inversion) conduction, and short-channel effects that dominate modern nanometer devices.
• N-channel enhancement only. One device type at fixed parameters. Depletion-mode, P-channel, and the body (substrate-bias) effect on V_th are not shown.
• No second-order non-idealities. Gate-oxide leakage/tunneling, hot-carrier effects, temperature dependence, and breakdown are ignored; the gate is treated as a perfect insulator with I_g = 0.
• No parasitics or dynamics at speed. Gate, drain, and overlap capacitances are not circuit-modeled; the "frequency lag" lab is a qualitative animation, not an RC/transient solve.
• Arbitrary units. K, V_th ≈ 2 V, and currents are illustrative constants, not extracted from a real process; the I-V curves convey shape, not datasheet values.
• Single transistor. No load-line interaction beyond a fixed load resistor, no CMOS pair, and no real circuit topology (biasing networks, current mirrors, etc.).