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This interactive tutorial visualizes the three stages of LDPC Rate Matching: Bit Selection, Bit Interleaving, and Bit Concatenation (output). The simulation uses a single code block with Base Graph 2 (BG2) and a circular buffer of length Ncb.
Mathematical foundation1. Circular buffer (w) The interleaved LDPC coded bits are mapped to the circular buffer w of length Ncb. For BG2 without limited buffer rate matching, Ncb = N = 52·Zc. The first 2·Zc bits are punctured (never transmitted). Systematic bits occupy the next 8·Zc positions (some may be filler <NULL>); the rest are parity bits. 2. Starting index k0 For BG2, k0 = ⌊(offset[rvid] · Ncb) / (50·Zc)⌋ · Zc, with offsets [0, 13, 25, 43] for RV 0, 1, 2, 3. 3. Bit Selection (5.4.2.1) Select E bits from w starting at index k0, wrapping around if needed. Filler bits (value −1) are skipped and do not count toward E. 4. Bit Interleaving (5.4.2.2) The E selected bits are written row-by-row into a matrix with C′ columns (e.g. from modulation order), then read column-by-column to form the final output.
2
100
= 0
50
Systematic
Parity
Punctured (2·Zc)
Filler
Window of Selection
Step detailWaiting to start selection…
Waiting to start interleaving…
Key parameters (3GPP TS 38.212 §5.4.2)
Input bits (code block)d0, d1, d2, …, dN−1 (N = Ksb·Zc − fcnt; Ksb=22 for BG1, Ksb=10 for BG2; fcnt = length of filler bits). Current: N = —
d0 … dN−1:
Circular buffer wLength Ncb — Window of Selection from k0 for E bits
Where each colored section in the circular buffer comes from (3GPP TS 38.212)
Buffer construction: Punctured (Red, 2·Zc) → Systematic (Green) → Filler (Grey, fcnt) → Parity (Cyan/Blue) up to Ncb. Click "Animate Bit Selection" or "Step Fwd" to see step-by-step status.
Bit SelectionParameters for bit selection: LBRM (Table 5.4.2.1-1) and k0 (Table 5.4.2.1-2). Bit selection output e (e1, e2, …, eE−1): Table 5.4.2.1-1: Limited buffer rate matching (LBRM)
Table 5.4.2.1-2: k0 (Ncb = —, Zc = —)
Bit InterleavingMatrix based on Qm (C′ columns). Write row-by-row, read column-by-column (5.4.2.2). Click "Animate Interleaving", "Step Bwd", or "Step Fwd" to see step-by-step status.
Final Output: Serialized bitstream fk (length E) = f0, f1, …, fE−1Bit Interleaving output f: the final sequence sent to the modulator (3GPP TS 38.212 §5.4.2.2).
UsageUse this simulation to explore 3GPP TS 38.212 Section 5.4.2 LDPC Rate Matching:
Tips: Start with Zc=2 and E=100. Change Qm to see matrix rows change (e.g. Qm=6 → R′ = ⌈100/6⌉ = 17 rows). Change RV to see k0 shift the selection window. Parameters
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