This tutorial explains the 5G NR Gold sequence generator as a mechanism, not just as a stream of random-looking bits. The generator has two 31-bit shift registers, x1 and x2. Their output bits are XORed to create the scrambling sequence c(n).

The important idea is that the sequence is deterministic. If transmitter and receiver use the same c_init, they build the same x2 initial state and therefore generate the same scrambling bits.

Mathematical Foundation

The 5G Gold sequence is defined by three equations. The first equation tells how to produce the scrambling bit. The next two equations tell how to update the two shift registers.

This means the scrambling bit c(n) is the XOR of one bit from x1 and one bit from x2, after applying the Nc offset. Since addition modulo 2 is XOR, this is the same as c(n) = x1(n + Nc) XOR x2(n + Nc). In the simulator, after initialization, the current output positions are shown as the leftmost register cells:

This is the feedback rule for the first 31-bit register. To create the next bit entering the end of x1, take tap position 0 and tap position 3, XOR them, shift the register, and insert the result at the far end. In the simulator this appears as x1 feedback = x1[0] XOR x1[3].

This is the feedback rule for the second 31-bit register. To create the next bit entering x2, XOR tap positions 0, 1, 2, and 3. In the simulator this appears as x2 feedback = x2[0] XOR x2[1] XOR x2[2] XOR x2[3].

Therefore each Step does two things in order: first it reads x1[0] and x2[0] to output c(n), then it computes the two feedback bits and shifts both registers.

1. Build c_init

For a PDSCH-style example, this page uses:

For example, if n_RNTI = 1, q = 0, and n_ID = 0: c_init = 1 × 32768 + 0 × 16384 + 0 = 32768.

2. Load two registers

The first register is fixed:

x1(0)=1, x1(1)=0, ... , x1(30)=0

The second register is loaded from c_init. Bit i of c_init becomes x2(i), with the least significant bit loaded into x2(0).

3. Generate one scrambling bit

The current output is c(n) = x1(n + Nc) XOR x2(n + Nc), shown in the register view as:

4. Shift with feedback

After producing the output bit, both registers shift and append a new feedback bit:

5. Nc warm-up

5G NR uses Nc = 1600. That means the generator is shifted 1600 times before the first used scrambling bit c(0). The simulator lets you either start after Nc, as in the real procedure, or start from n=0 for easier learning.

Simulation

The interactive simulator is below. Use the controls to explore the concepts described above.

 

Usage Instructions

1. Preset: Select a starting example. The PDSCH presets fill n_RNTI, q, n_ID, and c_init.
2. Apply: Recompute c_init from n_RNTI, q, and n_ID using the PDSCH-style formula.
3. c_init: Edit this directly for a custom sequence. Press Initialize after changing it.
4. Start: Choose whether Initialize performs the Nc=1600 warm-up or starts from the raw initial registers.
5. Step Fwd / Step Bwd / Run: Generate bits one at a time, move backward through generated history, or run continuously.
6. Step details: Click the tutorial step buttons to see the calculation relevant to that stage.

What To Notice

The output bit is read before the shift. Therefore each Step first computes c(n) = x1[0] XOR x2[0], appends that bit to the stream, and then shifts both registers.

The yellow tap bits decide the next feedback bit. The green-outlined bit is the current output bit.

Parameters

Parameter	Meaning
n_RNTI	RNTI used by the PDSCH-style c_init formula.
q	Codeword index, either 0 or 1.
n_ID	Scrambling identity used in the c_init formula.
c_init	31-bit decimal value loaded into x2.
Nc	Warm-up offset of 1600 shifts before the first used scrambling bit.

Limitations

• Generator only, not a full scrambler. This page produces the sequence c(n); it does not show the downstream step of XOR-ing c(n) with actual PDSCH/PDCCH bits.
• One c_init mapping. Only the PDSCH-style c_init = n_RNTI·215 + q·214 + n_ID is built; other channels (PUSCH, PBCH, DM-RS, CSI-RS) use different c_init expressions not covered here.
• 31-bit registers, finite view. The animation visualizes a handful of taps and steps for clarity; it is a teaching view of the LFSRs, not an optimized bit-generation routine.
• Optional warm-up. The simulator lets you skip the Nc = 1600 warm-up for easier learning, which produces bits that do not match the real 5G NR sequence — use the warm-up option for spec-accurate output.