The PIC16 is an 8-bit microcontroller by Microchip with RISC instruction set. This page is a browser-based teaching model: you can type a small subset of assembly, single-step or run it, and see the W register, the STATUS register, data memory (SRAM), and Flash (program listing) update together with an 18-pin DIP drawing where PORTB pins glow when driven high (output).

Harvard Architecture

The PIC16 uses a Harvard-style organization: program memory (Flash, 14-bit words) and data memory (SRAM, 8-bit file registers) are separate address spaces. Instructions are fetched from Flash; MOVLW, ADDWF, MOVWF, etc. operate on the data side.

Instruction cycle (conceptual)

Each Step Fwd performs FETCH → DECODE → EXECUTE: the current Flash line is highlighted, then registers / I/O / flags update. Run repeats steps at a selectable rate (Hz). Step Bwd restores the previous snapshot (limited history) for experimentation.

Memory map (simplified visualization)

Region	Contents
W Register	The Working register, implicitly used in many instructions
File Registers (SRAM)	Memory-mapped files: STATUS at 0x03, PORTA at 0x05, PORTB at 0x06, TRISB at 0x86 (modeled functionally / flat for simplicity)
I/O space	MOVWF 0x06 drives PORTB; pins RB0–RB7 light up
Program Flash	Up to 8K of 14-bit instructions

ALU and STATUS

ADDWF, SUBWF update flags Z DC C. Z (zero), DC (digit carry), C (carry / borrow) are shown as lit tiles when set. BTFSS / BTFSC skip the next instruction based on bit status.

Simulation

The interactive simulator is below. Use the controls to explore the concepts described above.

 

Usage

1. Load & Reset — Parses the assembly text area into Flash, resets registers, SRAM, I/O, PC, and STATUS.
2. Step Fwd / Step Bwd — Execute one instruction forward or undo one step.
3. Run / Stop — Continuous stepping at Simulation speed (Hz).
4. Chip view — Red glow on DIP pins corresponding to RB0–RB7.
5. Memory tabs — SRAM shows the file registers. Flash listing shows source lines; current PC line is highlighted.
6. Comments — Lines starting with ; are ignored.

Opcodes (subset)

NOP · MOVLW k · MOVWF f · MOVF f, d · ADDLW k · ADDWF f, d · SUBLW k · SUBWF f, d · BSF f, b · BCF f, b · BTFSC f, b · BTFSS f, b · GOTO k.

Limitations

This is for visualization and learning. Timers, exact multi-bank handling, full EEPROM and peripheral configuration, or cycles are simplified.