Syncrhonization

Two SDRs sharing one 10 MHz cable are not necessarily fully synchronized. I assumed they were for a long time, and the direction-finding results proved otherwise. Synchronization is four separate problems, and a shared reference clock solves only the first of them. Each section below covers one mechanism, in the order the problems have to be solved. Each section also names the hardware that implements it, because a datasheet and a bench often disagree.

• Executive Summary
• What exactly has to be synchronized, and in what order?
• How does a shared reference clock work, and what does it leave unsolved?
• What does a PPS signal add that a reference clock cannot?
• What does a GNSS disciplined oscillator change?
• Why is phase coherence harder than frequency and time?
• How do timed commands align the first sample?
• How is the radio synchronized with the software stack above it?
• Where does a transmit timestamp come from?
• How are the uplink and the downlink synchronized on one radio?
• How is it done when the radios are far apart?
• Where does time actually come from, and who is the master?
• What happens when the timing master fails?
• What can each SDR on the market actually do?
• How do you verify that two SDRs are really synchronized?
• Reference

Executive Summary

The table is a lookup. Each row is one mechanism, and the third column is the reason no single row is enough on its own.

What exactly has to be synchronized, and in what order?

You can get two receivers to show the same signal and still fail a coherent measurement. Before connecting cables, decide whether the experiment needs matching frequencies, matching sample times, or a known phase relationship.

Frequency synchronization makes the clocks run at the same rate. A relative error of 1 ppm means 3,500 Hz at a 3.5 GHz carrier. The same fractional error means 30.72 samples per second at 30.72 MS/s. These are calculated examples, not accuracy specifications for a particular radio. A fixed sample offset cannot correct an offset that keeps growing.

Epoch synchronization gives the counters a common origin. Both radios must agree which physical instant has the label zero, or a chosen absolute second. Sample alignment then places corresponding samples on that time axis. Matching timestamps alone cannot prove that the analogue paths have equal delay.

Phase coherence adds another requirement. The receiver channels must maintain a known relative RF phase over the measurement interval. Equal carrier frequency prevents a steady phase rotation, but it does not remove an initial phase offset. Cables, filters and mixers also contribute phase.

For a practical setup, establish frequency first, assign the epoch, schedule acquisition, and measure the remaining channel mismatch. Absolute UTC is optional for a local array. Relative agreement between channels is essential. Two independently accurate clocks can still be less useful than one shared clock for that array.

• Define the required relationship. Frequency agreement, sample alignment and phase coherence need different evidence.
• Calibrate after synchronization. Hardware timing establishes a common basis; measurement removes the remaining path offsets.

How does a shared reference clock work, and what does it leave unsolved?

A 10 MHz connector can look like a complete synchronization interface. It supplies a periodic reference, though, and the radio still has to derive its working clocks and decide when its counter starts.

The clock circuitry locks selected internal clocks to the external reference. A 10 MHz reference does not require a 10 MS/s sample rate. The radio derives other frequencies through its clock tree and rate conversion. Configure compatible rates on both radios and read back the actual rates accepted by the driver.

The diagram below separates the reference distribution from the PPS distribution. Each radio derives its sample clock from 10 MHz. Each counter uses PPS as a common edge, with its numerical time assigned separately by software.

Figure 1. A common reference controls clock rate; PPS and software establish the shared time labels.

• The blue paths feed the clock trees. They do not assign a counter value.
• The brown paths deliver the same PPS edge. Cable and distribution delays affect its arrival time.

Check the electrical interface before treating reference inputs as interchangeable. HackRF One expects a 10 MHz signal on CLKIN and detects it when an RX or TX operation begins. Its clock output must also be enabled. Other products use different input levels or termination arrangements. A connected cable therefore does not prove reference selection or lock.

• Read the lock status. Verify the selected source after configuration and during the experiment.
• A shared reference leaves an epoch problem. Continue with a common edge and a deliberate counter initialization.

What does a PPS signal add that a reference clock cannot?

Imagine two clocks ticking at exactly the same rate but displaying different seconds. PPS gives both radios a recurring physical event, so software can attach the same counter value to the same event.

PPS means one pulse per second. The selected edge marks a boundary; the pulse itself does not say which second it represents. You can assign zero for a laboratory experiment or use a time value supplied by a timing receiver. In the latter case, check whether the receiver's message describes the preceding edge or the next one.

On supported USRPs, set_time_next_pps() arms a counter update for the next PPS. Arm all boards with sufficient margin before the same edge. If configuration crosses that edge, one board can update a second later. Read back the latched PPS time on each board before accepting synchronization.

The physical edge also takes time to travel. For example, coax with propagation velocity 0.67 times the speed of light introduces about 5 ns per metre. This is a cable example, not a universal PPS accuracy. Distribution skew, input detection and clock-domain capture contribute additional error.

PPS does not keep two independent oscillators at the same frequency between edges. Also, resetting counters does not automatically start the two receive streams together. Combine the reference and epoch configuration with a common future stream start. Measure RF path delay separately when the application needs antenna-level alignment.

• The edge and its label are separate. Verify both PPS arrival and the assigned second.
• Equal cable lengths reduce one error term. They do not establish the complete end-to-end timing accuracy.

What does a GNSS disciplined oscillator change?

You cannot run a short reference cable between sites several kilometres apart. A GNSS disciplined oscillator provides a local frequency reference and a time reference, allowing each site to operate from satellite timing.

The local oscillator supplies the continuous clock. A control loop adjusts it using GNSS observations. This separates short-term oscillator behaviour from long-term timing correction. The output can continue when satellite reception disappears, but its error then depends on the oscillator and its holdover control.

A GPSDO therefore has several states worth recording: acquisition, locked operation and holdover. A running 10 MHz output is not proof of GNSS lock. The receiver needs an appropriate antenna installation and adequate satellite visibility. Indoor equipment can use an outdoor antenna; indoor placement does not automatically imply holdover.

OctoClock-G combines an internal GPSDO with distribution to multiple devices. A shared local distribution system still has cable-delay errors. Two independent GPSDOs add their separate timing errors as well. Neither arrangement directly measures the RF phase through the complete receiver chains.

Time representation needs attention too. GPS time, UTC and TAI are different time scales. Confirm the scale supplied by the timing equipment and the scale expected by the application. A correctly aligned PPS can accompany an incorrectly labelled second. Do not hard-code a time-scale offset without managing its validity.

Specify an allowable error over the intended observation interval. Then check the particular GPSDO's locked and holdover specifications under their stated conditions. There is no single accuracy number that applies to every GNSS disciplined SDR installation.

• GNSS distributes a time reference between sites. It does not remove local cable and RF path delays.
• Record timing quality with the samples. Lock state and holdover age explain otherwise surprising measurement changes.

Why is phase coherence harder than frequency and time?

Two aligned recordings can have identical waveforms with different complex phases. That difference matters in beamforming and direction finding, because the algorithm interprets relative phase as information about the signal's propagation.

A frequency reference constrains oscillator rate. It does not generally fix the startup phase of every synthesizer and divider. Shared LO hardware removes an independent oscillator from part of the system, but cables, filters and mixers still contribute channel-dependent phase. Retuning or restarting can change the result.

For a narrowband calibration, feed a common signal into both receivers through a splitter. After aligning samples, estimate phi = arg(sum(xB[n] * conj(xA[n]))). With this definition, multiply channel B by exp(-j * phi) to remove its measured phase offset relative to A. Estimate amplitude mismatch as well if the application needs calibrated complex gain.

A single tone cannot uniquely identify an arbitrary time delay. Delay produces phase that varies with frequency, and a tone measures only one point of that relationship. Use a broadband signal or multiple suitable frequencies to estimate delay across the operating band. Include splitter and cable differences in the calibration model.

Observe the phase over time rather than taking one estimate. A residual frequency difference produces a phase slope of 2 * pi * delta_f radians per second. Noise and temperature changes can add variation. Repeat the measurement after changes to tuning, filters, clock configuration or cabling, and establish how long the calibration remains useful.

• Stable phase need not be zero phase. A constant offset can be measured and corrected.
• Separate delay from phase. One complex rotation cannot correct a broadband timing mismatch.

How do timed commands align the first sample?

Calling start twice from a host gives the radios two different arrival times. A timed start instead names a future radio time, so each device can wait locally for the intended event.

First configure rates and reference sources, wait for lock, and establish the common epoch. Then choose a future start with enough margin for every device. For UHD reception, the stream command uses stream_now = false and a time_spec. The host must issue it before the deadline.

A timed TX burst uses transmit metadata with a valid time specification. Queue the samples early enough for the device to retain them until the requested start. Continuing the burst also requires a sustainable data supply; an accurate first timestamp cannot prevent a later underrun.

Do not assume that every timed operation has sample-period resolution. UHD converts command times into hardware ticks, and execution granularity depends on the FPGA implementation. General timed commands also execute in queue order. They are not sorted into chronological order after arrival.

Late behaviour depends on the operation. UHD reports a late RX stream command through RX metadata. Late TX packets can produce an asynchronous time error. A late general timed command can execute immediately instead. Check the relevant result rather than assuming every late operation is silently discarded.

These mechanisms align digital operations. RF settling and analogue path delay remain separate. Start calibration only after the radio has settled into the configuration that the experiment will actually use.

• Send early, execute at radio time. The host call time is not the sample time.
• Check the operation's timing support. Stream commands and general control commands have different restrictions.

How is the radio synchronized with the software stack above it?

The software stack receives samples after the radio captured them. USB transfers, network packets and host scheduling all add delay, so packet arrival at the application cannot identify the original sampling instant.

The adaptor must preserve the relationship between sample position and radio time. In UHD RX metadata, time_spec identifies the first sample, when the time specification is valid. For a continuous block, sample n then belongs to t0 + n / fs. The application needs the actual configured sample rate fs.

Suppose a block contains 30,720 samples at 30.72 MS/s. It spans 1 ms of sample time. The next contiguous block begins at t0 + 1 ms, even if the operating system delivers both blocks during one host scheduling interval. Buffering changes delivery time without changing the original sample times.

Continuity must be checked. Overflow, missing packets or a restarted stream can invalidate simple sample counting across blocks. Compare the next valid timestamp with the expected value. Preserve error metadata and mark gaps explicitly instead of joining unrelated samples into an apparently continuous slot.

The host also needs a clock for measuring processing duration. That clock serves a different purpose from the radio counter. A host monotonic timer can measure how long decoding took, but its numerical value cannot be copied directly into a device timestamp.

This division belongs in the adaptor interface: samples, their first-sample time, their count and any discontinuity status. The stack can then derive frame or slot boundaries from a defined radio-time origin.

• Transport delay does not redefine sample time. Preserve timestamps through buffering and processing.
• A gap breaks continuous counting. Recover the time relationship from valid metadata before continuing.

Where does a transmit timestamp come from?

A stack often schedules transmission relative to received radio time. This avoids treating the host wall clock as the radio clock, but the received timestamp describes an earlier capture, not the device's current time.

Let t_rx identify the first sample of a received block. A future transmit target can be written as t_tx = t_rx + K / fs, where K is a chosen sample offset. The protocol determines the intended event. The implementation must complete processing and delivery before that event.

The example below uses 30.72 MS/s and K = 92,160 samples, giving a 3 ms offset. Assume the complete TX payload reaches the device at radio time 10.0018 s. The remaining margin is 1.2 ms. These are illustrative timing values, not measurements of a particular host interface.

Figure 2. A correct TX timestamp is useful only when the samples arrive before its deadline.

• The blue interval represents capture time, not the time of the host receive call.
• The orange interval includes the remaining processing and delivery in this example.
• The green interval is scheduling margin. Its size depends on actual completion time.

If software computes the target from the end of the RX block, it must account for the block length. Mixing first-sample and end-of-block conventions introduces a full block of timing error. Larger lead times help only when the protocol allows them; they cannot arbitrarily move a scheduled radio event.

• Name the timestamp origin. State whether an offset starts at the first sample or after the block.
• Measure deadline margin under load. Average transport latency does not describe the worst processing interval.

How are the uplink and the downlink synchronized on one radio?

A shared counter lets one radio name both receive and transmit events. It does not make the two analogue paths equally long, and that distinction becomes visible when a stack schedules over-the-air boundaries.

At a base station, downlink uses the TX path and uplink uses the RX path. At a UE, those directions reverse. Keep that role explicit when interpreting a trace. A timestamp at the digital interface is not automatically the instant when the waveform crosses the antenna connector.

Interpolation, decimation, digital filters and analogue filters contribute delay. The useful correction relates the driver's timestamp reference point to the physical reference point required by the application. Document the sign and units of that correction. Configuration interfaces may express it in samples, time units or a device-specific form.

A loopback measurement estimates the combined transmit, cable and receive delay. Subtract a known cable delay when appropriate. A single loopback measurement does not independently identify the TX and RX contributions. Separate calibration information is needed if those contributions must be corrected individually.

TDD adds switching constraints. The transmit path, receive path and external RF switches need suitable settling and guard intervals. FDD can operate both directions simultaneously, but it still has path-delay differences. Radio path calibration also differs from the UE timing advance that compensates uplink propagation timing.

Repeat the delay check after changing the sample rate or filter configuration. A correction measured in samples changes its time meaning when the sample rate changes, even before any hardware delay changes are considered.

• Specify the physical timing reference. Digital sample time and antenna time need an explicit relationship.
• Loopback measures a sum. Do not assign the entire measured delay to one direction without additional evidence.

How is it done when the radios are far apart?

Long distances make direct clock distribution inconvenient. Network timing can distribute frequency and time, but its performance depends on the clocks, timestamping hardware and network path rather than the Ethernet connector alone.

PTP exchanges timing messages to estimate clock offset and path delay. Hardware timestamping places measurements closer to the physical interface and avoids much software scheduling variation. Path asymmetry still matters. In a simple symmetric-delay estimator, a forward/reverse delay difference of 200 ns produces a 100 ns offset error.

SyncE distributes frequency through the Ethernet physical layer. It does not by itself assign an epoch. White Rabbit combines frequency distribution with timing exchange and calibrated link-delay handling. Ordinary Ethernet switches and an arbitrary PTP configuration do not automatically provide the same behaviour.

Ettus documents White Rabbit configurations for N3xx with specific FPGA images and optical links. In the documented setup, SFP0 carries timing rather than IQ streaming. Its reported sub-nanosecond PPS measurements describe that laboratory setup; they are not a guarantee of RF phase alignment for every N3xx installation.

Keep network clock error separate from sample-delivery delay. A correctly synchronized radio can still receive a transmit packet too late. Conversely, prompt packet delivery cannot repair a counter that uses the wrong epoch. The synchronization network and the sample transport therefore need separate verification.

For separated coherent receivers, include antenna cables and RF calibration in the timing budget. Accurate timestamps help locate an observation in time, but they cannot independently reveal the unknown phase of each receiver chain.

• SyncE supplies frequency; time needs more. Verify the supported timing protocol and profile for each endpoint.
• Network timing and delivery are separate budgets. Measure clock error and packet deadline margin independently.

Where does time actually come from, and who is the master?

The word master hides several different responsibilities. One device can supply frequency, another can identify absolute seconds, and the host can choose the future sample time at which an experiment begins.

The frequency source determines the rate at which the local counter advances. A crystal, OCXO or rubidium reference can perform that role. Its stability does not tell the application the calendar date. The epoch source supplies the relationship between a counter value and an agreed event.

A trigger source has a narrower role. It asks armed devices to begin an operation at a physical edge. HackRF's clock master and trigger master need not be the same device. This is useful when one unit distributes frequency while another controls acquisition.

The operating system has further clocks. A network interface can have a PTP hardware clock, while the host maintains its own system clock. LinuxPTP's phc2sys synchronizes clocks such as these. That operation does not automatically discipline an attached SDR's independent FPGA counter. The radio needs an actual supported timing connection or clock-control mechanism.

For a local test, assign a common arbitrary zero and record how it was established. For measurements across sites, document the time scale and the source of absolute seconds. Also identify which device becomes the source after a failure. An undocumented automatic source change can make two apparently healthy instruments follow different references.

A useful setup record lists the frequency source, epoch source, trigger source and LO arrangement separately. It then states how software reads each relevant status.

• A stable oscillator does not supply a date. Frequency and absolute time are separate properties.
• Trace each clock domain. Host, NIC and radio synchronization require explicit connections.

What happens when the timing master fails?

A radio can keep producing samples after losing its timing reference. That continuity is useful, but it can also hide a growing synchronization error unless the application records timing quality alongside the stream.

During holdover, the local oscillator maintains the clock without its normal disciplining input. For a constant fractional frequency error epsilon, accumulated time error is approximately epsilon multiplied by elapsed time. For example, 25 ppb over 60 seconds gives 1.5 microseconds. This is a calculation, not an OctoClock-G holdover specification.

Real error can also change with temperature, ageing and the quality of the previous frequency estimate. Two radios in holdover need not drift in the same direction. Their relative timing error depends on the difference between their oscillator errors.

Source switching creates another problem. A replacement source may have a different phase or epoch. A device might slew gradually, step its counter, lose lock temporarily or require reinitialization. Check the actual implementation. Never infer uninterrupted coherent operation merely because an automatic backup source exists.

Define the application's permitted holdover interval from its timing tolerance. Record the loss-of-lock instant, the selected replacement source and any counter discontinuity. Stop accepting coherent measurements when the tolerance can no longer be supported, even if ordinary sample streaming continues.

After reference recovery, verify counters and sample continuity before scheduling new bursts. Recheck RF calibration if the clock tree or synthesizers restarted. Data captured during the transition should carry a quality indication that survives later processing.

• Holdover is a timed condition. Its usefulness depends on oscillator error and the application's tolerance.
• Recovery needs verification. Restored lock alone does not prove restored phase calibration.

What can each SDR on the market actually do?

Product families expose different parts of the synchronization problem. The examples below distinguish a shared clock, a timed digital interface and RF coherence; the exact board, daughterboard and FPGA image still matter.

A connector list is only the first check. Read the driver behaviour and the clock topology too. A two-channel device may share one LO within a receive pair while using a separate LO for transmission. Two such devices do not automatically extend that sharing across chassis.

For other boards, ask the same specific questions: can software read hardware sample time, schedule a future start, detect gaps and observe reference lock? Then check whether LO sharing or a repeatable calibration path exists. These capabilities determine the usable experiment more reliably than a generic claim of MIMO support.

• Check the complete configuration. Board name alone does not establish synchronization capability.
• Distinguish channel sharing from chassis sharing. Internal coherence features may not extend to a second device.

How do you verify that two SDRs are really synchronized?

A lock indicator answers only one question about the setup. To verify the complete system, measure frequency, time and RF phase separately, then repeat the measurements under the conditions of the actual experiment.

Begin with source selection and status. Record the actual sample rates, reference lock, PPS activity and assigned epoch. Compare exported timing edges where the hardware supports them. Account for probe and cable delay before interpreting a small measured skew.

Next, feed a common known waveform into both receive paths through a splitter. Use appropriate attenuation and respect the receiver input limits. Cross-correlate the recordings to estimate relative delay. Measure fractional delay or phase across frequency when integer-sample alignment is insufficient.

Track the complex phase difference over a longer interval. A constant offset suggests a calibration term. A steady slope suggests residual frequency error, while discontinuities suggest a restart, sample gap or configuration event. These are diagnostic clues; correlate them with status and error logs before assigning a cause.

Exercise the host path as well. Run the intended sample rate and channel count under representative processing load. Count RX discontinuities, TX time errors and underruns. Successful timestamp initialization says nothing about whether the application can continuously meet its deadlines.

Finally, repeat after a power cycle, retune and reference interruption. State the measured delay, phase variation, observation duration and configuration in the result. For TX verification, observe the actual output with a suitable independent receiver or instrument rather than relying only on a successful send call.

• Measure at the required reference point. PPS skew, sample timestamps and antenna phase are different results.
• Test repeatability and sustained operation. One aligned burst does not prove a stable coherent system.

Reference

The list below is where the numbers and the device behaviour on this page come from. The vendor documentation is the authority for anything specific to a board, and the specifications are the authority for the network mechanisms.

• HackRF External Clock Interface : Great Scott Gadgets - CLKIN and CLKOUT levels, the 10 MHz requirement, and the detection behaviour at the start of an operation.
• HackRF Hardware Triggering / HackRF Synchronization Checklist : Great Scott Gadgets - the P28 trigger header and the order of operations for multi-device capture.
• Synchronization and MIMO Capability with USRP Devices : Ettus Research - reference and PPS distribution, and the timed command sequence.
• OctoClock CDA-2990 : Ettus Research - eight-way 10 MHz and PPS distribution, internal GPSDO and source selection.
• TwinRX Daughterboard : Ettus Research - LO sharing across two daughterboards for four phase-coherent receive channels.
• Ethernet-Based Synchronization on the USRP N3xx : Ettus Research - White Rabbit on SFP0, the measured skew and the loss of the port for data.
• UHD Device Synchronization : Clock and epoch setup, timed stream starts and phase-alignment limitations.
• UHD Timed Commands : Command queues, hardware time quantization and late general-command execution.
• UHD RX Metadata, TX Metadata and Asynchronous Metadata : First-sample timestamps, timed bursts, discontinuities and TX error events.
• UHD B2x0 Manual : Clock inputs, timed sampling, B210 LO sharing and master clock rate changes.
• LinuxPTP phc2sys : Synchronizing host and PTP hardware clocks.
• Synchronizing multiple AD9361 devices : Analog Devices - multi-chip synchronization, the MCS RF enable bit and the 0 and 180 degree LO ambiguity.
• KrakenSDR : KrakenRF - five common-clocked RTL-SDR receivers, the 1 ppm reference and the onboard switched noise source for automatic phase calibration.
• 3GPP TS 38.104 : NR base station radio transmission and reception. Further reading for applicable base-station timing requirements; no numerical compliance limits are reproduced here.
• O-RAN.WG4.CUS.0 : O-RAN Alliance - Further reading on open-fronthaul control, user and synchronization planes; no profile-specific requirements are reproduced here.
• ShareTechnote - Adaptors/Connectors : The fronthaul and host interfaces that carry the synchronization described here.
• ShareTechnote - RU-DU Interface : The open fronthaul interface, including the S-plane.
• ShareTechnote - The Real-Time Loop : The slot loop that consumes the sample stream, and why a stack counts samples instead of reading a timer.
• ShareTechnote - Memory and Buffering : The buffer chain on each host interface, and the overflow and underrun conditions behind the UHD markers.
• ShareTechnote - SDR Hardware : Boards and their connectors.